(1) Field of the Invention
The present invention relates to a processor system including a processor and a coprocessor. The present invention particularly relates to techniques to control transfer of data used to perform an operation and data obtained as a result of an operation, between the coprocessor that performs a predetermined operation and the processor.
(2) Description of the Related Art
A conventional computing system includes a processor system. This processor system has a general purpose processor (hereinafter referred to as “a main processor”) and a processor for a specific operation (hereinafter referred to as “a coprocessor”), and is configured so that these processors operate in cooperation with each other.
Such a processor system including a main processor and a coprocessor is, for example, utilized for a video image encoding process in accordance with the Moving Picture Experts Group (MPEG) format.
This video image encoding process involves calculations, a large part of which are motion estimation (ME) processes. Here, ME requires calculation of absolute differences, for each piece of pixel data, between the frames constituting a video image to be encoded, and calculation of the sum of the absolute differences, and the calculations are generally performed based on a great deal of pieces or pixel data. Therefore, a very large number of operations are performed in relation to the calculation of absolute differences and the sum of the absolute differences.
Hence, absolute differences and the sum of the absolute differences are calculated by the coprocessor that has an arithmetic and logic unit (ALU) designed exclusively for performing calculations in parallel, and other processes necessary for the encoding process are performed by the main processor. In this way, the number of clock cycles (hereinafter simply referred to as “cycles”) required to complete the entire encoding process is reduced.
As stated above, this processor system in which the main processor and coprocessor operate in cooperation with each other can naturally complete a desired process within a smaller number of cycles than a processor system formed by using a single processor. Accordingly, this processor system can complete the desired process even with a relatively low operating frequency.
Generally speaking, a high cost is inevitable for technological development in order to increase an operating frequency of a processor system. Therefore, the reduction in number of cycles produces an effect that a relatively low-cost processor system can be employed to perform a desired process. In addition, a low operating frequency produces an effect of low power consumption.
Here, it has been conventionally known that instructions to cause the coprocessor to perform an operation include a coprocessor data processing instruction and a coprocessor register transfer instruction. The coprocessor register transfer instruction instructs transfer of data used to perform an operation and data obtained as a result of an operation between the main processor and coprocessor (see “KAITEI ARM PROCESSOR (ARM PROCESSOR REDACTED)” by Steve Furber, translated into Japanese under supervision of ARM Ltd., issued on December 18 in Japan, 2001 (1st edition), CQ publishing Co., Ltd., pages 122-126).
The coprocessor register transfer instruction instructs one-way data transfer between the main processor and coprocessor.
In more detail, the coprocessor register transfer instruction can designate a register in the main processor, in terms of only one of data used to perform an operation, i.e. source data, and data obtained as a result of an operation, i.e. destination data.
FIG. 17 illustrates an example of a program to cause the coprocessor to perform an operation.
In the program shown in FIG. 17, the instruction MCR in the line L1 is a coprocessor register transfer instruction that indicates transfer of data to the coprocessor, and gives an instruction to the coprocessor. The instruction MCR includes a first operand “p0”, a second operand “0”, a third operand “r1”, a fourth operand “Cr1”, and a fifth operand “Cr2”. The first operand specifies the coprocessor. The second operand specifies an operation to be performed by the coprocessor. Here, the second operand having a value “0” indicates that the coprocessor is to perform a specific operation requiring three cycles. The third operand specifies a register in the main processor which stores data used to perform the operation, i.e. source data. The fourth and fifth operands specify registers in the coprocessor which are to be used to perform the operation. The instructions “nop” in the lines L2 and L3 instruct no particular operations, and respectively consume one cycle. The instruction MRC in the line L4 is a coprocessor register transfer instruction that indicates transfer of data from the coprocessor, and gives an instruction to the coprocessor. The instruction MRC includes a first operand “p0”, a second operand “1”, a third operand “r0”, a fourth operand “Cr1”, and a fifth operand “Cr2”. The first operand specifies the coprocessor. The second operand specifies an operation to be performed by the coprocessor. Here, the second operand having a value “1” indicates that the coprocessor is to perform no operation. The third operand specifies a register in the main processor which is to store data obtained as a result of an operation, i.e. destination data. The fourth and fifth operands specify registers in the coprocessor which are used to perform an operation.
As described above, two coprocessor register transfer instructions are issued for transfer of source data and transfer of destination data, when the coprocessor performs an operation based on the source data stored in the main processor, and the main processor stores the destination data generated as a result of the operation performed by the coprocessor.